Reticle size limitations are forcing chip design teams to look beyond a single SoC or processor in order to achieve orders of magnitude improvements in processing that are required for AI. But moving data between more processing elements adds a whole new set of challenges that need to be addressed at multiple levels. Steve Woo, distinguished inventor and fellow at Rambus, examines the benefits of a common substrate for communication, the impact of pre-processing data in or near memory, and how to mitigate thermal effects in these new super chips.
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- Source: https://semiengineering.com/the-road-to-super-chips/